Aldas Nabazas
16 years ago
committed by
Alejandro Mery
11 changed files with 214 additions and 53049 deletions
File diff suppressed because it is too large
Load Diff
@ -1,579 +0,0 @@
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# --- SDE-COPYRIGHT-NOTE-BEGIN ---
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# This copyright note is auto-generated by ./scripts/Create-CopyPatch.
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#
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# Filename: package/.../gcc/niagara.patch
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# Copyright (C) 2006 The T2 SDE Project
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#
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# More information can be found in the files COPYING and README.
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#
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# This patch file is dual-licensed. It is available under the license the
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# patched project is licensed under, as long as it is an OpenSource license
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# as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
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# of the GNU General Public License as published by the Free Software
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# Foundation; either version 2 of the License, or (at your option) any later
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# version.
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# --- SDE-COPYRIGHT-NOTE-END ---
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2006-03-02 David S. Miller <davem@sunset.davemloft.net>
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Sun Niagara specific optimizations.
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* config.gcc: Recognize niagara as target.
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* config/sparc/sparc.h (SPARC_RELAXED_ORDERING): Mention Niagara.
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(TARGET_CPU_niagara): Define.
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(CPP_CPU64_DEFAULT_SPEC): Define __sparc_v9__ for Niagara.
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(ASM_CPU64_DEFAULT_SPEC): Pass -Av9b for Niagara.
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(CPP_CPU_SPEC): Handle -mcpu=niagara.
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(ASM_CPU_SPEC): Likewise.
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(PROCESSOR_NIAGARA): New enum entry.
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(REGISTER_MOVE_COST): Handle Niagara.
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(BRANCH_COST, PREFETCH_BLOCK, SIMULTANEOUS_PREFETCHES): Likewise.
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* config/sparc/sparc.c (niagara_costs): New processor_costs entry.
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(sparc_override_options): Recognize "niagara", set appropriate
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default MASK_* values for it, and align functions to 32-bytes
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by default just like ULTRASPARC/ULTRASPARC3.
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(sparc_initialize_trampoline): Handle niagara like ultrasparc.
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(sparc64_initialize_trampoline): Likewise.
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(sparc_use_sched_lookahead): Use zero for niagara.
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(sparc_issue_rate): Use one for niagara.
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* config/sparc/niagara.md: New file.
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* config/sparc/sparc.md: Include it.
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* config/sparc/sol2-bi.h (CPP_CPU64_DEFAULT_SPEC,
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ASM_CPU32_DEFAULT_SPEC, ASM_CPU64_DEFAULT_SPEC): Set appropriately
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when default cpu is niagara.
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(CPP_CPU_SPEC): Handle -mcpu=niagara.
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(ASM_CPU_SPEC): Likewise.
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* config/sparc/sol2.h (ASM_CPU_DEFAULT_SPEC): Set appropriately
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when default cpu is niagara.
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(ASM_CPU_SPEC): Handle -mcpu=niagara.
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* config/sparc/linux64.h: Handle a default of TARGET_CPU_niagara
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just like v9/ultrasparc/ultrasparc3.
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* doc/invoke.texi: Add documentation for "niagara" and improve
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existing documentation for ultrasparc variants.
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Index: gcc/config.gcc
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===================================================================
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--- ./gcc/config.gcc (revision 111647)
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+++ ./gcc/config.gcc (working copy)
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@@ -2830,7 +2830,7 @@
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"" | sparc | sparcv9 | sparc64 | sparc86x \
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| v7 | cypress | v8 | supersparc | sparclite | f930 \
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| f934 | hypersparc | sparclite86x | sparclet | tsc701 \
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- | v9 | ultrasparc | ultrasparc3)
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+ | v9 | ultrasparc | ultrasparc3 | niagara)
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# OK
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;;
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*)
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Index: gcc/config/sparc/linux64.h
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===================================================================
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--- ./gcc/config/sparc/linux64.h (revision 111647)
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+++ ./gcc/config/sparc/linux64.h (working copy)
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@@ -43,7 +43,8 @@
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#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
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|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
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- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
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+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
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+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
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/* A 64 bit v9 compiler with stack-bias,
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in a Medium/Low code model environment. */
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Index: gcc/config/sparc/niagara.md
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===================================================================
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--- ./gcc/config/sparc/niagara.md (revision 0)
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+++ ./gcc/config/sparc/niagara.md (revision 0)
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@@ -0,0 +1,119 @@
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+;; Scheduling description for Niagara.
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+;; Copyright (C) 2006 Free Software Foundation, Inc.
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+;;
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+;; This file is part of GCC.
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+;;
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+;; GCC is free software; you can redistribute it and/or modify
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+;; it under the terms of the GNU General Public License as published by
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+;; the Free Software Foundation; either version 2, or (at your option)
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+;; any later version.
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+;;
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+;; GCC is distributed in the hope that it will be useful,
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+;; but WITHOUT ANY WARRANTY; without even the implied warranty of
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+;; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+;; GNU General Public License for more details.
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+;;
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+;; You should have received a copy of the GNU General Public License
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+;; along with GCC; see the file COPYING. If not, write to
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+;; the Free Software Foundation, 51 Franklin Street, Fifth Floor,
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+;; Boston, MA 02110-1301, USA.
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+
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+;; Niagara is a single-issue processor.
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+
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+(define_automaton "niagara_0")
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+
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+(define_cpu_unit "niag_pipe" "niagara_0")
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+
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+(define_insn_reservation "niag_5cycle" 5
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "multi,flushw,iflush,trap"))
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+ "niag_pipe*5")
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+
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+(define_insn_reservation "niag_4cycle" 4
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "savew"))
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+ "niag_pipe*4")
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+
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+/* Most basic operations are single-cycle. */
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+(define_insn_reservation "niag_ialu" 1
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "ialu,shift,compare,cmove"))
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+ "niag_pipe")
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+
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+(define_insn_reservation "niag_imul" 11
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "imul"))
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+ "niag_pipe*11")
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+
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+(define_insn_reservation "niag_idiv" 72
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "idiv"))
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+ "niag_pipe*72")
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+
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+(define_insn_reservation "niag_branch" 3
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "call,sibcall,call_no_delay_slot,uncond_branch,branch"))
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+ "niag_pipe*3")
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+
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+(define_insn_reservation "niag_3cycle_load" 3
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "load"))
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+ "niag_pipe*3")
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+
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+(define_insn_reservation "niag_9cycle_load" 9
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fpload"))
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+ "niag_pipe*9")
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+
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+(define_insn_reservation "niag_1cycle_store" 1
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "store"))
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+ "niag_pipe")
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+
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+(define_insn_reservation "niag_8cycle_store" 8
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fpstore"))
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+ "niag_pipe*8")
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+
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+/* Things incorrectly modelled here:
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+ * FPADD{s,d}: 26 cycles
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+ * FPSUB{s,d}: 26 cycles
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+ * FABSD: 26 cycles
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+ * F{s,d}TO{s,d}: 26 cycles
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+ * F{s,d}TO{i,x}: 26 cycles
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+ * FSMULD: 29 cycles
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+ */
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+(define_insn_reservation "niag_fmov" 8
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fpmove,fpcmove,fpcrmove"))
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+ "niag_pipe*8")
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+
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+(define_insn_reservation "niag_fpcmp" 26
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fpcmp"))
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+ "niag_pipe*26")
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+
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+(define_insn_reservation "niag_fmult" 29
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fpmul"))
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+ "niag_pipe*29")
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+
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+(define_insn_reservation "niag_fdivs" 54
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fpdivs"))
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+ "niag_pipe*54")
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+
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+(define_insn_reservation "niag_fdivd" 83
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fpdivd"))
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+ "niag_pipe*83")
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+
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+/* Things incorrectly modelled here:
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+ * FPADD{16,32}: 10 cycles
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+ * FPSUB{16,32}: 10 cycles
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+ * FALIGNDATA: 10 cycles
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+ */
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+(define_insn_reservation "niag_vis" 8
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+ (and (eq_attr "cpu" "niagara")
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+ (eq_attr "type" "fga,fgm_pack,fgm_mul,fgm_cmp,fgm_pdist"))
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+ "niag_pipe*8")
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Index: gcc/config/sparc/sol2-bi.h
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===================================================================
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--- ./gcc/config/sparc/sol2-bi.h (revision 111647)
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+++ ./gcc/config/sparc/sol2-bi.h (working copy)
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@@ -39,6 +39,15 @@
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#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
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#endif
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+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
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+#undef CPP_CPU64_DEFAULT_SPEC
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+#define CPP_CPU64_DEFAULT_SPEC ""
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+#undef ASM_CPU32_DEFAULT_SPEC
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+#define ASM_CPU32_DEFAULT_SPEC "-xarch=v8plusb"
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+#undef ASM_CPU64_DEFAULT_SPEC
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+#define ASM_CPU64_DEFAULT_SPEC AS_SPARC64_FLAG "b"
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+#endif
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+
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#if DEFAULT_ARCH32_P
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#define DEF_ARCH32_SPEC(__str) "%{!m64:" __str "}"
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#define DEF_ARCH64_SPEC(__str) "%{m64:" __str "}"
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@@ -57,7 +66,7 @@
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%{mcpu=sparclite|mcpu-f930|mcpu=f934:-D__sparclite__} \
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%{mcpu=v8:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
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%{mcpu=supersparc:-D__supersparc__ " DEF_ARCH32_SPEC("-D__sparcv8") "} \
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-%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
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+%{mcpu=v9|mcpu=ultrasparc|mcpu=ultrasparc3|mcpu=niagara:" DEF_ARCH32_SPEC("-D__sparcv8") "} \
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%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
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"
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@@ -66,7 +75,8 @@
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%{mcpu=v9:" DEF_ARCH32_SPEC("-xarch=v8plus") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "} \
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%{mcpu=ultrasparc:" DEF_ARCH32_SPEC("-xarch=v8plusa") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "a") "} \
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%{mcpu=ultrasparc3:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
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-%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}} \
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+%{mcpu=niagara:" DEF_ARCH32_SPEC("-xarch=v8plusb") DEF_ARCH64_SPEC(AS_SPARC64_FLAG "b") "} \
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+%{!mcpu=niagara:%{!mcpu=ultrasparc3:%{!mcpu=ultrasparc:%{!mcpu=v9:%{mcpu*:" DEF_ARCH32_SPEC("-xarch=v8") DEF_ARCH64_SPEC(AS_SPARC64_FLAG) "}}}}} \
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%{!mcpu*:%(asm_cpu_default)} \
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"
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Index: gcc/config/sparc/sol2.h
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===================================================================
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--- ./gcc/config/sparc/sol2.h (revision 111647)
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+++ ./gcc/config/sparc/sol2.h (working copy)
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@@ -1,6 +1,6 @@
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/* Definitions of target machine for GCC, for SPARC running Solaris 2
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- Copyright 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2004, 2005
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- Free Software Foundation, Inc.
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+ Copyright 1992, 1995, 1996, 1997, 1998, 1999, 2000, 2001, 2002, 2004, 2005,
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+ 2006 Free Software Foundation, Inc.
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Contributed by Ron Guilmette (rfg@netcom.com).
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Additional changes by David V. Henkel-Wallace (gumby@cygnus.com).
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@@ -41,11 +41,17 @@
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#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
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#endif
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+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
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+#undef ASM_CPU_DEFAULT_SPEC
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+#define ASM_CPU_DEFAULT_SPEC "-xarch=v8plusb"
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+#endif
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+
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#undef ASM_CPU_SPEC
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#define ASM_CPU_SPEC "\
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%{mcpu=v9:-xarch=v8plus} \
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%{mcpu=ultrasparc:-xarch=v8plusa} \
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%{mcpu=ultrasparc3:-xarch=v8plusb} \
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+%{mcpu=niagara:-xarch=v8plusb} \
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%{!mcpu*:%(asm_cpu_default)} \
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"
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Index: gcc/config/sparc/sparc.c
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===================================================================
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--- ./gcc/config/sparc/sparc.c (revision 111647)
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+++ ./gcc/config/sparc/sparc.c (working copy)
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@@ -197,6 +197,30 @@
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0, /* shift penalty */
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};
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+static const
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+struct processor_costs niagara_costs = {
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+ COSTS_N_INSNS (3), /* int load */
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+ COSTS_N_INSNS (3), /* int signed load */
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+ COSTS_N_INSNS (3), /* int zeroed load */
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+ COSTS_N_INSNS (9), /* float load */
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+ COSTS_N_INSNS (8), /* fmov, fneg, fabs */
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+ COSTS_N_INSNS (8), /* fadd, fsub */
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+ COSTS_N_INSNS (26), /* fcmp */
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+ COSTS_N_INSNS (8), /* fmov, fmovr */
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+ COSTS_N_INSNS (29), /* fmul */
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+ COSTS_N_INSNS (54), /* fdivs */
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+ COSTS_N_INSNS (83), /* fdivd */
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+ COSTS_N_INSNS (100), /* fsqrts - not implemented in hardware */
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+ COSTS_N_INSNS (100), /* fsqrtd - not implemented in hardware */
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+ COSTS_N_INSNS (11), /* imul */
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+ COSTS_N_INSNS (11), /* imulX */
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+ 0, /* imul bit factor */
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+ COSTS_N_INSNS (72), /* idiv */
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+ COSTS_N_INSNS (72), /* idivX */
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+ COSTS_N_INSNS (1), /* movcc/movr */
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+ 0, /* shift penalty */
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+};
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+
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const struct processor_costs *sparc_costs = &cypress_costs;
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#ifdef HAVE_AS_RELAX_OPTION
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@@ -597,6 +621,7 @@
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{ TARGET_CPU_v9, "v9" },
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{ TARGET_CPU_ultrasparc, "ultrasparc" },
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{ TARGET_CPU_ultrasparc3, "ultrasparc3" },
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+ { TARGET_CPU_niagara, "niagara" },
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{ 0, 0 }
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};
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const struct cpu_default *def;
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@@ -632,6 +657,8 @@
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/* TI ultrasparc III */
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/* ??? Check if %y issue still holds true in ultra3. */
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{ "ultrasparc3", PROCESSOR_ULTRASPARC3, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
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+ /* UltraSPARC T1 */
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+ { "niagara", PROCESSOR_NIAGARA, MASK_ISA, MASK_V9|MASK_DEPRECATED_V8_INSNS},
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{ 0, 0, 0, 0 }
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};
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const struct cpu_table *cpu;
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@@ -741,7 +768,8 @@
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/* Supply a default value for align_functions. */
|
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if (align_functions == 0
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&& (sparc_cpu == PROCESSOR_ULTRASPARC
|
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- || sparc_cpu == PROCESSOR_ULTRASPARC3))
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+ || sparc_cpu == PROCESSOR_ULTRASPARC3
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+ || sparc_cpu == PROCESSOR_NIAGARA))
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align_functions = 32;
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/* Validate PCC_STRUCT_RETURN. */
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@@ -790,6 +818,9 @@
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case PROCESSOR_ULTRASPARC3:
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sparc_costs = &ultrasparc3_costs;
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break;
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+ case PROCESSOR_NIAGARA:
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+ sparc_costs = &niagara_costs;
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+ break;
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||||
};
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||||
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#ifdef TARGET_DEFAULT_LONG_DOUBLE_128
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@@ -7099,7 +7130,8 @@
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aligned on a 16 byte boundary so one flush clears it all. */
|
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emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode, tramp))));
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if (sparc_cpu != PROCESSOR_ULTRASPARC
|
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- && sparc_cpu != PROCESSOR_ULTRASPARC3)
|
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+ && sparc_cpu != PROCESSOR_ULTRASPARC3
|
||||
+ && sparc_cpu != PROCESSOR_NIAGARA)
|
||||
emit_insn (gen_flush (validize_mem (gen_rtx_MEM (SImode,
|
||||
plus_constant (tramp, 8)))));
|
||||
|
||||
@@ -7141,7 +7173,8 @@
|
||||
emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, tramp))));
|
||||
|
||||
if (sparc_cpu != PROCESSOR_ULTRASPARC
|
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- && sparc_cpu != PROCESSOR_ULTRASPARC3)
|
||||
+ && sparc_cpu != PROCESSOR_ULTRASPARC3
|
||||
+ && sparc_cpu != PROCESSOR_NIAGARA)
|
||||
emit_insn (gen_flushdi (validize_mem (gen_rtx_MEM (DImode, plus_constant (tramp, 8)))));
|
||||
|
||||
/* Call __enable_execute_stack after writing onto the stack to make sure
|
||||
@@ -7321,6 +7354,8 @@
|
||||
static int
|
||||
sparc_use_sched_lookahead (void)
|
||||
{
|
||||
+ if (sparc_cpu == PROCESSOR_NIAGARA)
|
||||
+ return 0;
|
||||
if (sparc_cpu == PROCESSOR_ULTRASPARC
|
||||
|| sparc_cpu == PROCESSOR_ULTRASPARC3)
|
||||
return 4;
|
||||
@@ -7336,6 +7371,7 @@
|
||||
{
|
||||
switch (sparc_cpu)
|
||||
{
|
||||
+ case PROCESSOR_NIAGARA:
|
||||
default:
|
||||
return 1;
|
||||
case PROCESSOR_V9:
|
||||
Index: gcc/config/sparc/sparc.h
|
||||
===================================================================
|
||||
--- ./gcc/config/sparc/sparc.h (revision 111647)
|
||||
+++ ./gcc/config/sparc/sparc.h (working copy)
|
||||
@@ -1,6 +1,6 @@
|
||||
/* Definitions of target machine for GNU compiler, for Sun SPARC.
|
||||
Copyright (C) 1987, 1988, 1989, 1992, 1994, 1995, 1996, 1997, 1998, 1999
|
||||
- 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
|
||||
+ 2000, 2001, 2002, 2003, 2004, 2005, 2006 Free Software Foundation, Inc.
|
||||
Contributed by Michael Tiemann (tiemann@cygnus.com).
|
||||
64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
|
||||
at Cygnus Support.
|
||||
@@ -206,7 +206,7 @@
|
||||
which requires the following macro to be true if enabled. Prior to V9,
|
||||
there are no instructions to even talk about memory synchronization.
|
||||
Note that the UltraSPARC III processors don't implement RMO, unlike the
|
||||
- UltraSPARC II processors.
|
||||
+ UltraSPARC II processors. Niagara does not implement RMO either.
|
||||
|
||||
Default to false; for example, Solaris never enables RMO, only ever uses
|
||||
total memory ordering (TMO). */
|
||||
@@ -238,10 +238,12 @@
|
||||
#define TARGET_CPU_sparc64 7 /* alias */
|
||||
#define TARGET_CPU_ultrasparc 8
|
||||
#define TARGET_CPU_ultrasparc3 9
|
||||
+#define TARGET_CPU_niagara 10
|
||||
|
||||
#if TARGET_CPU_DEFAULT == TARGET_CPU_v9 \
|
||||
|| TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc \
|
||||
- || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3
|
||||
+ || TARGET_CPU_DEFAULT == TARGET_CPU_ultrasparc3 \
|
||||
+ || TARGET_CPU_DEFAULT == TARGET_CPU_niagara
|
||||
|
||||
#define CPP_CPU32_DEFAULT_SPEC ""
|
||||
#define ASM_CPU32_DEFAULT_SPEC ""
|
||||
@@ -262,6 +264,10 @@
|
||||
#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
|
||||
#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
|
||||
#endif
|
||||
+#if TARGET_CPU_DEFAULT == TARGET_CPU_niagara
|
||||
+#define CPP_CPU64_DEFAULT_SPEC "-D__sparc_v9__"
|
||||
+#define ASM_CPU64_DEFAULT_SPEC "-Av9b"
|
||||
+#endif
|
||||
|
||||
#else
|
||||
|
||||
@@ -352,6 +358,7 @@
|
||||
%{mcpu=v9:-D__sparc_v9__} \
|
||||
%{mcpu=ultrasparc:-D__sparc_v9__} \
|
||||
%{mcpu=ultrasparc3:-D__sparc_v9__} \
|
||||
+%{mcpu=niagara:-D__sparc_v9__} \
|
||||
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(cpp_cpu_default)}}}}}}} \
|
||||
"
|
||||
#define CPP_ARCH32_SPEC ""
|
||||
@@ -401,6 +408,7 @@
|
||||
%{mcpu=v9:-Av9} \
|
||||
%{mcpu=ultrasparc:%{!mv8plus:-Av9a}} \
|
||||
%{mcpu=ultrasparc3:%{!mv8plus:-Av9b}} \
|
||||
+%{mcpu=niagara:%{!mv8plus:-Av9b}} \
|
||||
%{!mcpu*:%{!mcypress:%{!msparclite:%{!mf930:%{!mf934:%{!mv8:%{!msupersparc:%(asm_cpu_default)}}}}}}} \
|
||||
"
|
||||
|
||||
@@ -524,7 +532,8 @@
|
||||
PROCESSOR_TSC701,
|
||||
PROCESSOR_V9,
|
||||
PROCESSOR_ULTRASPARC,
|
||||
- PROCESSOR_ULTRASPARC3
|
||||
+ PROCESSOR_ULTRASPARC3,
|
||||
+ PROCESSOR_NIAGARA
|
||||
};
|
||||
|
||||
/* This is set from -m{cpu,tune}=xxx. */
|
||||
@@ -2137,7 +2146,8 @@
|
||||
|| (GENERAL_OR_I64 (CLASS1) && FP_REG_CLASS_P (CLASS2)) \
|
||||
|| (CLASS1) == FPCC_REGS || (CLASS2) == FPCC_REGS) \
|
||||
? ((sparc_cpu == PROCESSOR_ULTRASPARC \
|
||||
- || sparc_cpu == PROCESSOR_ULTRASPARC3) ? 12 : 6) : 2)
|
||||
+ || sparc_cpu == PROCESSOR_ULTRASPARC3 \
|
||||
+ || sparc_cpu == PROCESSOR_NIAGARA) ? 12 : 6) : 2)
|
||||
|
||||
/* Provide the cost of a branch. For pre-v9 processors we use
|
||||
a value of 3 to take into account the potential annulling of
|
||||
@@ -2147,22 +2157,30 @@
|
||||
|
||||
On v9 and later, which have branch prediction facilities, we set
|
||||
it to the depth of the pipeline as that is the cost of a
|
||||
- mispredicted branch. */
|
||||
+ mispredicted branch.
|
||||
|
||||
+ On Niagara, normal branches insert 3 bubbles into the pipe
|
||||
+ and annulled branches insert 4 bubbles. */
|
||||
+
|
||||
#define BRANCH_COST \
|
||||
((sparc_cpu == PROCESSOR_V9 \
|
||||
|| sparc_cpu == PROCESSOR_ULTRASPARC) \
|
||||
? 7 \
|
||||
: (sparc_cpu == PROCESSOR_ULTRASPARC3 \
|
||||
- ? 9 : 3))
|
||||
+ ? 9 \
|
||||
+ : (sparc_cpu == PROCESSOR_NIAGARA \
|
||||
+ ? 4 \
|
||||
+ : 3)))
|
||||
|
||||
#define PREFETCH_BLOCK \
|
||||
((sparc_cpu == PROCESSOR_ULTRASPARC \
|
||||
- || sparc_cpu == PROCESSOR_ULTRASPARC3) \
|
||||
+ || sparc_cpu == PROCESSOR_ULTRASPARC3 \
|
||||
+ || sparc_cpu == PROCESSOR_NIAGARA) \
|
||||
? 64 : 32)
|
||||
|
||||
#define SIMULTANEOUS_PREFETCHES \
|
||||
- ((sparc_cpu == PROCESSOR_ULTRASPARC) \
|
||||
+ ((sparc_cpu == PROCESSOR_ULTRASPARC \
|
||||
+ || sparc_cpu == PROCESSOR_NIAGARA) \
|
||||
? 2 \
|
||||
: (sparc_cpu == PROCESSOR_ULTRASPARC3 \
|
||||
? 8 : 3))
|
||||
Index: gcc/config/sparc/sparc.md
|
||||
===================================================================
|
||||
--- ./gcc/config/sparc/sparc.md (revision 111647)
|
||||
+++ ./gcc/config/sparc/sparc.md (working copy)
|
||||
@@ -1,6 +1,6 @@
|
||||
;; Machine description for SPARC chip for GCC
|
||||
;; Copyright (C) 1987, 1988, 1989, 1992, 1993, 1994, 1995, 1996, 1997, 1998,
|
||||
-;; 1999, 2000, 2001, 2002, 2003, 2004, 2005 Free Software Foundation, Inc.
|
||||
+;; 1999, 2000, 2001, 2002, 2003, 2004, 2005,2006 Free Software Foundation, Inc.
|
||||
;; Contributed by Michael Tiemann (tiemann@cygnus.com)
|
||||
;; 64-bit SPARC-V9 support by Michael Tiemann, Jim Wilson, and Doug Evans,
|
||||
;; at Cygnus Support.
|
||||
@@ -94,7 +94,8 @@
|
||||
sparclet,tsc701,
|
||||
v9,
|
||||
ultrasparc,
|
||||
- ultrasparc3"
|
||||
+ ultrasparc3,
|
||||
+ niagara"
|
||||
(const (symbol_ref "sparc_cpu_attr")))
|
||||
|
||||
;; Attribute for the instruction set.
|
||||
@@ -315,6 +316,7 @@
|
||||
(include "sparclet.md")
|
||||
(include "ultra1_2.md")
|
||||
(include "ultra3.md")
|
||||
+(include "niagara.md")
|
||||
|
||||
|
||||
;; Operand and operator predicates.
|
||||
Index: gcc/doc/invoke.texi
|
||||
===================================================================
|
||||
--- ./gcc/doc/invoke.texi (revision 111647)
|
||||
+++ ./gcc/doc/invoke.texi (working copy)
|
||||
@@ -12268,8 +12268,8 @@
|
||||
for machine type @var{cpu_type}. Supported values for @var{cpu_type} are
|
||||
@samp{v7}, @samp{cypress}, @samp{v8}, @samp{supersparc}, @samp{sparclite},
|
||||
@samp{f930}, @samp{f934}, @samp{hypersparc}, @samp{sparclite86x},
|
||||
-@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc}, and
|
||||
-@samp{ultrasparc3}.
|
||||
+@samp{sparclet}, @samp{tsc701}, @samp{v9}, @samp{ultrasparc},
|
||||
+@samp{ultrasparc3}, and @samp{niagara}.
|
||||
|
||||
Default instruction scheduling parameters are used for values that select
|
||||
an architecture and not an implementation. These are @samp{v7}, @samp{v8},
|
||||
@@ -12283,7 +12283,7 @@
|
||||
v8: supersparc, hypersparc
|
||||
sparclite: f930, f934, sparclite86x
|
||||
sparclet: tsc701
|
||||
- v9: ultrasparc, ultrasparc3
|
||||
+ v9: ultrasparc, ultrasparc3, niagara
|
||||
@end smallexample
|
||||
|
||||
By default (unless configured otherwise), GCC generates code for the V7
|
||||
@@ -12317,9 +12317,11 @@
|
||||
architecture. This adds 64-bit integer and floating-point move instructions,
|
||||
3 additional floating-point condition code registers and conditional move
|
||||
instructions. With @option{-mcpu=ultrasparc}, the compiler additionally
|
||||
-optimizes it for the Sun UltraSPARC I/II chips. With
|
||||
+optimizes it for the Sun UltraSPARC I/II/IIi chips. With
|
||||
@option{-mcpu=ultrasparc3}, the compiler additionally optimizes it for the
|
||||
-Sun UltraSPARC III chip.
|
||||
+Sun UltraSPARC III/III+/IIIi/IIIi+/IV/IV+ chips. With
|
||||
+@option{-mcpu=niagara}, the compiler additionally optimizes it for
|
||||
+Sun UltraSPARC T1 chips.
|
||||
|
||||
@item -mtune=@var{cpu_type}
|
||||
@opindex mtune
|
||||
@@ -12331,8 +12333,8 @@
|
||||
@option{-mtune=@var{cpu_type}}, but the only useful values are those
|
||||
that select a particular cpu implementation. Those are @samp{cypress},
|
||||
@samp{supersparc}, @samp{hypersparc}, @samp{f930}, @samp{f934},
|
||||
-@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc}, and
|
||||
-@samp{ultrasparc3}.
|
||||
+@samp{sparclite86x}, @samp{tsc701}, @samp{ultrasparc},
|
||||
+@samp{ultrasparc3}, and @samp{niagara}.
|
||||
|
||||
@item -mv8plus
|
||||
@itemx -mno-v8plus
|
||||
|
||||
@ -1,38 +0,0 @@
|
||||
# --- SDE-COPYRIGHT-NOTE-BEGIN ---
|
||||
# This copyright note is auto-generated by ./scripts/Create-CopyPatch.
|
||||
#
|
||||
# Filename: package/.../gcc/powerpc64-nonofp.patch
|
||||
# Copyright (C) 2005 - 2006 The T2 SDE Project
|
||||
#
|
||||
# More information can be found in the files COPYING and README.
|
||||
#
|
||||
# This patch file is dual-licensed. It is available under the license the
|
||||
# patched project is licensed under, as long as it is an OpenSource license
|
||||
# as defined at http://www.opensource.org/ (e.g. BSD, X11) or under the terms
|
||||
# of the GNU General Public License as published by the Free Software
|
||||
# Foundation; either version 2 of the License, or (at your option) any later
|
||||
# version.
|
||||
# --- SDE-COPYRIGHT-NOTE-END ---
|
||||
|
||||
--- gcc-4.0.2/gcc/config/rs6000/t-linux64.vanilla 2005-12-22 08:50:38.000000000 +0000
|
||||
+++ gcc-4.0.2/gcc/config/rs6000/t-linux64 2005-12-22 08:51:17.000000000 +0000
|
||||
@@ -8,13 +8,13 @@
|
||||
|
||||
SHLIB_MAPFILES += $(srcdir)/config/rs6000/libgcc-ppc64.ver
|
||||
|
||||
-MULTILIB_OPTIONS = m64/m32 msoft-float
|
||||
-MULTILIB_DIRNAMES = 64 32 nof
|
||||
+MULTILIB_OPTIONS = m64/m32
|
||||
+MULTILIB_DIRNAMES = 64 32
|
||||
MULTILIB_EXTRA_OPTS = fPIC mstrict-align
|
||||
-MULTILIB_EXCEPTIONS = m64/msoft-float
|
||||
-MULTILIB_EXCLUSIONS = m64/!m32/msoft-float
|
||||
+MULTILIB_EXCEPTIONS =
|
||||
+MULTILIB_EXCLUSIONS =
|
||||
-MULTILIB_OSDIRNAMES = ../lib64 ../lib nof
|
||||
-MULTILIB_MATCHES = $(MULTILIB_MATCHES_FLOAT)
|
||||
+MULTILIB_OSDIRNAMES = ../lib64 ../lib
|
||||
+MULTILIB_MATCHES =
|
||||
|
||||
# We want fine grained libraries, so use the new code to build the
|
||||
# floating point emulation libraries.
|
||||
Loading…
Reference in new issue